1. Field of the Invention
This invention relates to semiconductor chips. More particularly, it relates to the design of a semiconductor chip. Still more particularly, it relates to a system and method for providing power to the gates of a semiconductor chip.
2. Related Art
An essential part of any semiconductor chip is its internal power network. It is the internal power network that routes power and ground from the pins of the external packaging of the chip to the gates of the chip. In the past, engineers have built elaborated power networks to route power and ground from the top layer of a semiconductor chip down to the lowest layer of a semiconductor chip.
In a conventional system for providing power to the gates of a semiconductor chip, each layer of the chip comprises a series of long, parallel metal strips. The placement of the gates generally dictates the design of the lowest layer of the internal power network while Ohm's law dictates the design of the remaining layers of the internal power network. The gates of a typical chip are formed more or less uniformly across the entire base of a chip. This distribution of gates means that power and ground must be available everywhere at the lowest layer of the chip to power the gates. Conventionally, power and ground are made available at the lowest layer of a chip by depositing a series of long, parallel metal strips. The gates of the chip are formed between these long, parallel metal strips. This arrangement ensures that every gate has access to both power and ground. While any system or method that routes power from one layer of the chip to another layer of the chip, without excessive voltage drop, may be used to route power from the top of the chip down to the lowest layer of the chip, engineers have conventionally made every layer of the internal power network out of long, parallel metal strips. These long, parallel metal strips at each layer of the chip are electrically connected to one another using vias.
This conventional system and method of routing power from the top layer of the chip down to the lowest layer of the chip has many drawbacks, however. For example, the elaborate internal power networks built by engineers in the past occupy a significant portion of the total routing area of a semiconductor chip. Using known internal power networks therefore significantly reduces the total routing area of a chip available for routing gate signal, and it complicates the design of a semiconductor chip. Furthermore, using known internal power networks makes semiconductor chips larger than they otherwise need to be and thereby increases the overall cost of a chip. Using known internal power networks also limits gate density.
What is needed is a simpler system and method for providing power to the gates of a semiconductor chip. As will be described in detail below, the present invention overcomes the drawbacks of the conventional system and method for providing power to the gates of a chip.